Vertical nano-ring gate transistors are the main candidate devices for integrated circuit technology of 2 nanometers and below, but they face many challenges in improving device performance and manufacturability. At the International Integrated Circuit Conference IEDM held at the end of 2018, Dr. Ryckaert1 from IMEC1 listed the control of the gate length and the relative position of the channel and the gate of the vertical nanodevice as one of the key challenges
Researcher Zhu Huilong from the Institute of Microelectronics Pilot Center and his research team have carried out systematic research on related basic devices and key processes since 2016, and proposed and implemented the world's first stacked vertical nano-ring-gate transistor with self-aligned gate ( VerticalSandwichGate-All-AroundFETs or VSAFETs), has obtained a number of Chinese and American invention patent authorizations, and the research results have recently been published in the top journal of the international microelectronic device field "IEEEElectronDeviceLetters" (DOI: 10.1109 / LED.2019.2954537)
A method for selective etching of SiGe at the atomic layer was developed systematically, and this method was used for the selective etching of SiGe / Si superlattice stacks in combination with multilayer epitaxial growth technology, so as to precisely control the nano-transistor trench Track size and effective gate length; first developed a self-aligned high-k metal gate back gate process for vertical nano-ring-gate transistors; its integrated process is compatible with mainstream advanced CMOS processes. The research team finally produced a p-type VSAFET with a gate length of 60 nanometers and a nanosheet thickness of 20 nanometers. The SS, DIBL and current switching ratio (Ion / Ioff) of the prototype device are 86mV / dec, 40mV and 1.8x105, respectively.